As is well-known in the art, class AB amplifiers are amplifiers containing circuits that are conductive only part of the time. As a result, class AB amplifiers generally have the advantage of using relatively little power. One prior art amplifier 10, which is described in an article entitled “An Integrated Low-Voltage Class AB CMOS OTA” by Ramesh Harjani, et al. and published in IEEE J. Solid-State, vol. 34, pp 134-142, February 1999, is shown in FIG. 1. The amplifier 10 is based on the principle of a self-biased input transistor. As shown in FIG. 1, two such NMOS transistors 12, 14 are combined in a common source configuration. The drains of the transistors 12, 14 are connected to the drains of respective NMOS transistors 16, 18, which have their gates connected to the gates of the transistors 12, 14, respectively. The transistors 16, 18 are connected to ground through respective current sinks 20, 22, and voltages VA, VB are generated at the sources of the transistors 16, 18, respectively. These voltages VA, VB are connected to an input of respective operational amplifiers 30, 32, which have their outputs connected to the gates of respective NMOS transistors 36, 38 that are connected in series with the transistors 12, 14. As further shown in FIG. 1, the transistors 12, 14 are connected in series with respective PMOS diode-connected transistors 40, 42, which have their gates coupled in current mirror fashion to respective transistor 46 and output transistor 48. The transistor 46 is, in turn, connected in series with a diode-connected NMOS transistor 50, and the output transistor 48 is connected in series with a diode-coupled output transistor 52, which have its gate coupled to the gate of the transistor 50. An output node 54 is formed at the interconnected drains of the transistors 48, 52.
In operation, when a differential input Vinp and Vinm, respectively, is zero, the voltages at the nodes designated VS, VA and VB are equal to common mode input voltage minus (VT+ΔV), where ΔV=√{square root over (2IB/K(W/L))} and VT is threshold voltage of the transistors 12, 14. Negative feedback ensures that the common source voltage of the transistors 12, 14 is always forced to track the smaller of the two voltages VA and VB, whereas VA and VB are (VT+ΔV) below Vinm and Vinp, respectively. More specifically, for example, if the input voltage Vinp is larger than the gate voltage Vinm, the voltage VB will be larger than VA. As a result, the output voltage of the operational amplifier 30 is effectively pulled down, which turns OFF the transistor 36. In such case, the current I1 through the transistor 14 is given by the formula:
                                                                        I                1                            =                                                1                  2                                ⁢                                  K                  ⁡                                      (                                          W                      L                                        )                                                  ⁢                                                      (                                          Vinp                      -                      VS                      -                      VT                                        )                                    2                                                                                                        =                                                1                  2                                ⁢                                  K                  ⁡                                      (                                          W                      L                                        )                                                  ⁢                                                      (                                          Vinp                      -                      VA                      -                      VT                                        )                                    2                                                                                        (                  Equation          ⁢                                          ⁢          1                )            where W/L is the channel width to length ratio of the transistor 14.
Further, using the relationship between VA and Vinm, i.e.,Vinm=VA+ΔV+VT  (Equation 2)where VT is the threshold voltage of the transistor 16.
The above Equation 1 for the current through the transistor 14 can be written as:
                              I          1                =                              1            2                    ⁢                      K            ⁡                          (                              W                L                            )                                ⁢                                    (                              Vinp                -                Vinm                +                                  Δ                  ⁢                                                                          ⁢                  V                                            )                        2                                              (                  Equation          ⁢                                          ⁢          3                )            
A slight difference between the input voltages Vinp and Vinm turns OFF one of the output transistors 46 or 48 and directs a large current, which is proportional to square of differential input voltage, Vinp−Vinm, to the other output transistor 48 or 46. The amplifier 10 is well suited for low-voltage applications. But, because all active loads are connected through diode-coupled transistors 46, 50 and 48, 52, the DC gain of the amplifier 10 is relatively low. As a result, the amplifier 10 is generally used only for low current application, which biases the transistors 46, 50 and 48, 52 to sub-threshold levels.
Attempts have been made to improve upon the amplifier 10 shown in FIG. 1 using an amplifier 60, which is shown in FIG. 2. This amplifier 60 is described in an article entitled “Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency” by Antonio J. Lopez-Martin, et al., which is published in IEEE J. Solid-State, vol. 40, pp 1068-1077, May 2005. The amplifier 60 includes a pair of PMOS input transistors 62, 64 receiving input voltages Vinm and Vinp, respectively. The transistors 62, 64 are coupled to ground through respective NMOS transistors 66, 68, which have their gates connected to each other and to their drains through respective feedback resistors 70, 72. A voltage “x” is generated at a node 74 formed by the interconnected drains of the transistors 62, 66, and a voltage “y” is generated at a node 76 formed by the interconnected drains of the transistors 64, 68. The voltage “x” is applied to the gate of an NMOS output transistor 80, which is connected in series with a diode-coupled PMOS transistor 82. Similarly, the voltage “y” is applied to the gate of an NMOS output transistor 84, which is connected in series with a PMOS transistor 86, which has its gate connected to the gate of the transistor 82. An output node 88 is formed at the interconnected drains of the transistors 84, 86. Finally, the respective sources and gates of the input transistors 62, 64 are connected to an adaptive biasing circuit 90, which is described in greater detail below.
In operation, the common mode voltage at the drain of the transistors 66, 68 is fed back to their common gates to provide additional current boosting. This technique is sometimes known as Local Common-Mode Feedback (“LCMFB”). The loads at the nodes 74, 76 where the voltages “x” and “y” are generated are approximately equal to the resistances of the feedback resistors 70, 72, respectively. Without the resistors 70, 72 the load at these nodes 74, 76 would be significantly smaller, i.e., on the order of 1/gm of the transistors 66, 68. This increased impedance at the nodes 74, 76 increases the DC gain of the amplifier 60. Furthermore, if the amplifier 60 drives a large capacitive load, which is common in many applications, the dominant pole of the amplifier is determined by the capacitance and is independent of the impedance of the resistors 70, 72.
A prior art circuit 100 used for the adaptive biasing circuit 90 in the prior art amplifier 60 is shown in FIG. 3. For purposes of brevity and simplicity, only one-half the circuit is shown in FIG. 3 along with the PMOS transistor 62. The circuit 100 uses a pair of PMOS transistors 102, 104 connected in series with a current sink 106 between VCC and the drain of the transistor 62. The gate of the transistor 102 is connected to the node between the source of the transistor 104 and the current source 106, and the gate of the transistor 104 is connected to the gate of the input transistor 62, as also shown in FIG. 2.
A variety of techniques are used in the prior art to connect the circuit 100 shown in FIG. 3 with another of the circuits 100. However all of these exhibit a significant problem. Specifically, since the transistor 102 is diode-connected, and because the electrical characteristics of the transistor 62 should duplicate the electrical characteristics of the transistor 104, therefore the common mode input voltage must be precisely controlled. Otherwise, the transistors 62, 104 operate in their triode or ohmic region rather than in their amplification region, which would adversely impact the gain of the amplifier 60 using the circuit 100. Therefore, if the circuit 100 is used in the amplifier 60, and the amplifier 60 is used as an input buffer, the differential input voltage must be within a very small range to prevent the transistors 62, 104 from operating in their triode or ohmic region. Furthermore, the limits of the acceptable range varies with supply voltage, process variations, temperature and current supply.
There is therefore a need for a class AB amplifier that has the desirable attributes of the amplifiers 10, 60 without the above-described disadvantages.